The present invention relates to a microprocessor executing a program by replacing an order of read and write.
A microprocessor, such as an image processing processor, occasionally executes a program by replacing an order of read and write. Such a microprocessor executes instructions by replacing the order of a read instruction and a write instruction that have been issued from a central processing unit (xe2x80x9cCPUxe2x80x9d) to a main memory or a peripheral system, according an order of a program, in order to improve a processing performance. According to this kind of microprocessor, when the CPU accesses a register, such as a control register in the peripheral system, but the meaning is different depending on the order of the access, it is necessary to guarantee an access order.
In general, the CPU carries out a processing (operation) by accessing a machine instruction or data that is stored in the main memory. However, because an operation speed of the main memory is extremely lower than that of the CPU, it takes a long processing time to read from and to write to the main memory. Therefore, a cache memory that operates at a higher speed than the main memory is provided between the CPU and the main memory. The instruction or data is temporarily stored in the cache memory, to reduce access to the main memory. Based on this arrangement, a processing time required for read and write is reduced.
FIG. 1 is a schematic diagram that shows an outline of a flow of the data when the CPU writes the data into the main memory. A microprocessor 1 has a CPU 2 and a cache system 3. The CPU 2 outputs a write data and a write address data (hereinafter, an address data will be simply referred to as an address) to the cache system 3. The write data and the write address are sent to a main memory 6 via a bus control section (xe2x80x9cBUSCxe2x80x9d) 5, and are written into the main memory 6. The solid black arrows in FIG. 1 show the flow of data when the CPU writes the data into the main memory.
FIG. 2 is a schematic diagram that shows an outline of a flow of data when the CPU 2 reads the data from the main memory 6. The CPU 2 outputs an address of the data to be read, that is, a read address, to the cache system 3. The read address is sent to the main memory 6 via the bus control section 5. The main memory 6 reads the data corresponding to the read address. The read data is sent to the CPU 2 via the bus control section 5 and the cache system 3. The solid black arrows in FIG. 2 show the flow of data when the CPU reads the data from the main memory 6.
FIG. 3 is a schematic diagram that shows another outline of the flow of the data when the CPU 2 writes the data into a peripheral system 7. The CPU 2 outputs the write data and the write address to the cache system 3. The write data and the write address are sent to the peripheral system 7, via the bus control section 5, and are written into a control register or the like. The solid black arrows in FIG. 3 show the flow of the data when the CPU 2 writes the data into the peripheral system 7.
FIG. 4 is a schematic diagram that shows an outline of the flow of the data when the CPU 2 reads the data from the peripheral system 7. The CPU 2 outputs the read address to the cache system 3. The read address is sent to the peripheral system 7 via the bus control section 5. The peripheral system 7 reads the data corresponding to the read address. The read data is sent to the CPU 2 via the bus control section 5 and the cache system 3. The solid black arrows in FIG. 4 show the flow of the data when the CPU 2 reads the data from the peripheral system 7.
FIG. 5 is a block diagram that shows a detailed structure of a cache system of a conventional microprocessor. As shown in FIG. 5, the cache system 3 has a tag RAM 31 that stores an identification address of a cache block, and a cache RAM 32 that stores the data.
The cache system 3 has a wait address register (xe2x80x9cWARxe2x80x9d) 33, a read address register (xe2x80x9cRARxe2x80x9d) 34, a cache write buffer address (xe2x80x9cCWBAxe2x80x9d) 35, and a store buffer address (xe2x80x9cSTBAxe2x80x9d) 36, as registers that store addresses. Further, the cache system 3 has a wait data register (xe2x80x9cWDRxe2x80x9d) 37, a cache write buffer (xe2x80x9cCWBxe2x80x9d) 38, and a store buffer (xe2x80x9cSTBxe2x80x9d) 39, as registers that store data. Further, the cache system 3 has five selectors 41, 43, 44, 45, and 46, and a tag address comparator 42. Further, the cache system 3 has a cache control section not shown that controls the cache system 3.
The operation of the microprocessor shown in FIG. 5 will be explained. FIG. 6 is a diagram that shows the flow of the address and a read data when a read access has a cache hit in the microprocessor shown in FIG. 5. In FIG. 6, thick lines show along which routes the address and the data flow (the same applies to FIG. 7 to FIG. 17, and FIG. 20 to FIG. 23). The CPU 2 supplies a read address to the tag RAM 31 and the cache RAM 32 via the selector 41. The tag address comparator 42 compares a tag address with the read address. When the tag address and the read address coincide with each other as a result of the comparison (cache hit), the CPU 2 receives the data that has been read from a way of the cache RAM 32 in which the addresses coincide, via the selectors 45 and 46. Further, a cache hit signal is asserted.
FIG. 7 is a diagram that shows the flow of the address and the read data when the read access has a cache miss in the microprocessor shown in FIG. 5. The CPU 2 supplies the read address to the tag RAM 31 via the selector 41. The tag address comparator 42 compares the tag address with the read address. When these do not coincide with each other as a result of the comparison (cache miss), the read address is stored into the read address register 34. The stored read address is output to the bus control section 5 together with a read request, until when the read address is accepted by the bus control section 5.
When the bus control section 5 has accepted the read request and the address, and the bus control section 5 has supplied the read data, the read data is sent to the CPU 2 via the selector 46, and the data is also stored into the cache RAM 32 via the selector 44. The cache hit signal is negated. More specifically, the read address is also supplied to the cache RAM 32 from the CPU 32. However, as the cache miss is explained in this case in FIG. 7, a thin line is used to show a section from the selector 41 to the cache RAM 32 instead of a thick line that shows an address supply route (the same applies to FIG. 15).
FIG. 8 is a diagram that shows the flow of the address and the read data when the write access has cache hit in the microprocessor shown in FIG. 5. The CPU 2 supplies a write address to the tag RAM 31 and the cache RAM 32 via the selector 41. The tag address comparator 42 compares the tag address with the write address. When the tag address and the write address coincide with each other as a result of the comparison (cache hit), the write address is stored into the cache write buffer address 35 and the store buffer address 36.
Further, the write data is stored into the cache write buffer 38 and the store buffer 39 via the selector 43. The write address stored in the store buffer address 36 and the write data stored in the store buffer 39 are supplied to the bus control section 5 together with a write request. On the other hand, the write address stored in the cache write buffer address 35 is supplied to the tag RAM 31 and the cache RAM 32. The write data stored in the cache write buffer 38 is written into an area corresponding to the write address of the cache RAM 32. Further, a cache hit signal is asserted.
FIG. 9 is a diagram that shows the flow of the address and the read data when the write access has cache miss in the microprocessor shown in FIG. 5. The CPU 2 supplies a write address to the tag RAM 31 via the selector 41. The tag address comparator 42 compares the tag address with the write address. When the tag address and the write address do not coincide with each other as a result of the comparison (cache miss), the write address is stored into the store buffer address 36. On the other hand, the write data is stored into the store buffer 39 via the selector 43.
The write request, the write address, and the write data are output to the bus control section 5 until the bus control section 5 accepts them. The cache hit signal is negated. More specifically, the write address is also supplied to the cache RAM 32 from the CPU 32. However, as the cache miss is explained in this case, a thin line is used to show a section from the selector 41 to the cache RAM 32 (the same applies to FIG. 20, FIG. 10, and FIG. 14).
Next, the operation will be explained when there is address dependency between write and read when the read access occurs following the write access in the microprocessor shown in FIG. 5. FIG. 10 to FIG. 13 are diagrams that sequentially show flows of an address and data in this case. The CPU 2 makes the write request to the cache system 3, and outputs the write address to the tag RAM 31. The tag address comparator 42 compares the tag address with the write address, and when there is a cache miss as a result of the comparison, the write address and a write data are stored into the store buffer address 36 and the store buffer 39 respectively. Then, the write request is output to the bus control section 5 (refer to FIG. 10).
The CPU 2 makes a read request to the cache system 3. Based on this read request, the read address is compared with the address stored in the store buffer address 36. When these addresses coincide with each other, the read address is stored into the wait address register 33. The read address is stored in the wait address register 33 until a preceding write request is accepted by the bus control section 5 and the operation is completed (refer to FIG. 11).
When the preceding write request has been completed, a succeeding read request is executed again. When the cache miss occurs, the read address is stored into the read address register 34, and the read request and the address are output to the bus control section 5 (refer to FIG. 12). The bus control section 5 accepts the read request, and returns the requested data to the cache system 3. The returned data is output from the cache system 3 to the CPU 2 (refer to FIG. 13). When there is an address dependency between the write access and the read access as explained above, the order of the write request and the read request is not replaced.
Next, the operation of an occasion in which there is no address dependency between write and read when the read access occurs following the write access in the microprocessor shown in FIG. 5, will be explained. FIG. 14 to FIG. 17 are diagrams that sequentially show flows of the address and the data in this case. The CPU 2 makes the write request to the cache system 3, and outputs the write address to the tag RAM 31. The tag address comparator 42 compares the tag address with the write address, and when there is a cache miss as a result of the comparison, the write address and the write data are stored into the store buffer address 36 and the store buffer 39, respectively. Then, the write request is output to the bus control section 5 (refer to FIG. 14).
The CPU 2 makes the read request to the cache system 3, and supplies the read address to the tag RAM 31. The tag address comparator 42 compares the addresses, and when there is a cache miss as a result of this comparison, the read address is stored into the read address register 34. The read request and the address are output to the bus control section 5 until the bus control section 5 accepts them (refer to FIG. 15).
As there is no address dependency between the preceding write request and the succeeding read request, the write request and the read request are output to the bus control section 5 at the same time. Normally, between the read request and the write request, a priority is placed to the read request that has a possibility of being used for the operation by the CPU 2. Therefore, the bus control section 5 first accepts the read request. Then, the bus control section 5 returns the requested data to the cache system 3. The returned data is supplied straight to the CPU 2 (refer to FIG. 16). The bus control section 5 then accepts the write request (refer to FIG. 17). When there is no address dependency between the write access and the read access as explained above, the order of the write request and the read request may be replaced in order to increase the processing capacity.
As explained above, it is not necessary to guarantee the access order to the access that has no address dependency. However, it is necessary to guarantee the access order to the access that is made to a register when the meaning is different depending on the access order, regardless of a presence or an absence of address dependency. For example, after data has been written into a timer control word register (TCTR) provided in the 8254 compatible timer of Intel Corporation, when data of a timer control status register (TCSR0 to 3) having a quite different address is read, the data may change.
In this timer control word register (xe2x80x9cTCTRxe2x80x9d), data becomes a read back command when a value of a select counter (xe2x80x9cSCxe2x80x9d) 1 or an SC0 is 11. When a value of the timer control status register (TCSR0 to 3) is read when the data is the read back command, the data becomes a status latched count value. On the hand, when a value of the timer control status register (TCSR0 to 3) is read when the data is not the read back command, that is, when a value of the SC1 or the SC0 is not 11, the data becomes a count value at that time.
Therefore, in an occasion of accessing these registers, in order to guarantee the access order, it is necessary to insert an instruction that waits for the completion of a loadistore instruction that has been executed before a main instruction like a xe2x80x9cmemberxe2x80x9d instruction, between the access to the timer control word register and the access to the timer control status register (TCSR0 to 3), as shown in FIG. 18, for example. In this case, the access order has conventionally been guaranteed based on software. However, in the compiler, it is difficult to output this kind of code, and therefore, it is necessary to describe a program for manually guaranteeing the access order. As a result, there has been a problem that the programming efficiency is poor.
It is an object of the present invention to provide a microprocessor that has a structure capable of guaranteeing an access order in hardware.
According to the present invention, the microprocessor is provided with a register which stores an address that requires a guarantee of an access order, and an address comparator which compares the address stored in the register with an address of an access request from a CPU. When the address comparator determines that the two addresses coincide with each other, a preceding access request is executed first, and a succeeding access request is executed after the preceding access request has been executed.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.